ARM Assembly

ARM Registers
While we haven't examined the x86_64 architecture yet, you will discover that the 32-bit implementation of ARM is much more similar to its 64-bit counterpart than the x86/i386 architecture is to its 64-bit x86_64/AMD64 counterpart. This is because ARM has kept much more parity developing the 32-bit and 64-bit implementations of its architecture. We will first be examining the common 32-bit registers used by ARMv7 or ARMv8 (when operating in 32-bit mode). As with Intel for the x86 processor, extensive documentation for the ARM architecture is available here.
It should also be noted that ARM devides its processors in to 3 profiles:
  1. a - Application profile, used for general purpose computing
  2. m - Microcontroller profile, used for small low-power applications such as sensors
  3. r - Real-time profile, used in applications that require predictable and consisting timing with processor results

ARM uses a version number to refer to the major revision of the architecture and instruction sets, such as v7, v8, v9, etc. Different versions may support either 32-bit or 64-bit operations, or both.

32-bit ARMv7 registers can be broken down as follows: 
	General purpose registers    Special Function Registers                         Program Status Registers (Similar to the x86 eflag register)   Floating point registers    
	r0                           r13 sp (stack pointer)   (equivalent to x86 esp)   cpsr (current program status register)                         32-bit (float)          
	r1                           r14 lr (link register)   (equivalent to x86 ebp)   spsr (saved program status register)                           s0 to s31          
	r2                           r15 pc (program counter) (equivalent to x86 eip)                                                                               
	r3                                                                                                                                             64-bit (double)          
	r4                                                                                                                                             d0 to d15
	r5
	r6
	r7
	r8
	r9
	r10
	r11
	r12
The flags for the cpsr are shown below: 
	bit 0x1F  1E  1D  1C  1B  1A  19  18  17    16   15   14  13  12  11  10  0F  0E  0D  0C  0B  0A  09  08  07  06  05  04  03  02  01  00
	flag  N   Z   C   V   Q   00  00  00  SSBS  PAN  DIT  00  |     GE     |  00  00  00  00  00  00  E   A   I   F   T   00  |     M      |
Below are the cpsr flag functions:
  • N: (Negative) flag, indicates whether the result of the last operation was negative (1) or positive (0)
  • Z: (Zero) flag, indicates whether the result of the last operation was zero (1) or not zero (0)
  • C: (Carry) flag, indicates whether there was a carry (1) or not (0) during the last arithmetic operation
  • V: (Overflow) flag, indicates whether an overflow occurred (1) or not (0) during the last arithmetic operation
  • Q (Saturation) flag, indicates whether saturation occurred (1) or not (0) during the last operation
  • SSBS (Speculative Store Bypass Safe) flag, indicates wether speculative loading of data is permitted (1) or not (0)
  • PAN (Privileged Access Never) flag, indicates wether privileged instructions can be executed in User mode (1) or not (0)
  • DIT (Data Independent Timing) flag, indicates if wether the processor can (0) execute instructions with timing independent timing of data processing or not (1)
  • GE (Greater than or equal), indicate the results of signed comparisons between operands
  • IT (If-Then) flags, indicate the execution state of the If-Then instruction
  • J (Jazelle) flag, indicates whether the processor is executing in Jazelle (Java support) mode (1) or not (0)
  • E (Endianness) flag, indicates the endianness of the processor, either little-endian (0) or big-endian (1)
  • A (Auxiliary carry), indicates whether there was a carry (1) or not (0) between the low nibble and high nibble during an 8-bit operation
  • I (Interrupt) flag, indicates whether maskable (optional) hardware interrupts should be processed (1) or not (0)
  • F (Fast Interrupt), indicates whether fast interrupt exceptions should be processed (1) or not (0)
  • T (Thumb) flag, indicates the execution state of the processor, either Thumb (1) or ARM (0)
  • M (Processor mode) flags, indicate the current processor mode, such as User, System, FIQ, IRQ, Supervisor, Abort, Undefined, or Monitor
While there are unique flags stored by ARM32 in the cpsr register, six of them are the same as in the x86 eflag: 
 Flag in ARM       Flag in x86           Flag
      N                 SF               Negative
      Z                 ZF               Zero
      C                 CF               Carry
      V                 OF               Overflow
      A                 AF               Auxiliary
      I                 IF               Interrupt
The spsr is used to save the state of the cpsr registers when the processor changes privilege modes. This frees the cpsr to load flags for the current state and allows the previous state to be restored later.